Towards White-Box Modeling of Hardware Transactional Memory Systems
نویسندگان
چکیده
This paper investigates the problem of deriving white box performance models of Hardware Transactional Memory (HTM) systems. The proposed model targets a popular implementation of HTM, i.e., the one integrated in Intel’s Xeon (Haswell family) processors, and focuses on capturing the dynamics of two key mechanisms: the concurrency control scheme and the management of transactional meta-data in the processor’s cache.
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تاریخ انتشار 2017